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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. october 2011 doc id 022405 rev 1 1/53 53 LIS3DSH mems digital output motion sensor ultra low-power high performance three-axis ?nano? accelerometer features wide supply voltage, 1.71 v to 3.6 v independent ios supply (1.8 v) and supply voltage compatible ultra low-power consumption 2 g /4 g / 6 g / 8 g/ 16 g dynamically selectable full-scale i 2 c/spi digital output interface 16-bit data output programmable embedded state machines embedded temperature sensor embedded self-test embedded fifo 10000 g high shock survivability ecopack ? rohs and ?green? compliant applications motion controlled user interface gaming and virtual reality pedometer intelligent power saving for handheld devices display orientation click/double click recognition impact recognition and logging vibration monitoring and compensation description the LIS3DSH is an ultra low-power high performance three-axis linear accelerometer belonging to the ?nano? family with embedded state machine that can be programmed to implement autonomous applications. the LIS3DSH has dynami cally selectable full scales of 2 g /4 g / 6 g / 8 g/ 16 g and it is capable of measuring accelerations with output data rates from 3.125 hz to 1.6 khz. the self-test capability a llows the user to check the functioning of the sensor in the final application. the device can be configured to generate interrupt signals activated by user defined motion patterns. the LIS3DSH has an integrated first in, first out (fifo) buffer allowing the user to store data for host processor intervention reduction. the LIS3DSH is available in a small thin plastic land grid array package (lga) and it is guaranteed to operate over an extended temperature range from -40 c to +85 c. table 1. device summary order codes temperature range [ c] package packaging LIS3DSH -40 to +85 lga-16 tray LIS3DSHtr -40 to +85 lga-16 tape and reel lga-16 (3x3x1 mm) www.st.com www.datasheet.co.kr datasheet pdf - http://www..net/
contents LIS3DSH 2/53 doc id 022405 rev 1 1 contents 1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3.2 i2c - inter ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6.1 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.8 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.4 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.5 retrieve data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH contents doc id 022405 rev 1 3/53 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 i2c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1.1 i2c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.1 info1 (0dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.2 info2 (0eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.4 ctrl_reg3 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.5 ctrl_reg4 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6 ctrl_reg5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.7 ctrl_reg6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.8 status (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.9 out_t (0ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.10 off_x (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.11 off_y (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.12 off_z (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.13 cs_x (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.14 cs_y (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.15 cs_z (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.16 lc (16h - 17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.17 stat (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.18 vfc_1 (1bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.19 vfc_2 (1ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.20 vfc_3 (1dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.21 vfc_4 (1eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.22 thrs3 (1fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.23 out_x (28h - 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 www.datasheet.co.kr datasheet pdf - http://www..net/
contents LIS3DSH 4/53 doc id 022405 rev 1 8.24 out_y (2ah - 2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.25 out_z (2ch - 2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.26 fifo_ctrl (2eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.27 fifo_src (2fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.28 ctrl_reg1 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.29 stx_1 (40h-4fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.30 tim4_1 (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.31 tim3_1 (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.32 tim2_1 (52h - 53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.33 tim1_1 (54h - 55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.34 thrs2_1 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.35 thrs1_1 (57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.36 mask1_b (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.37 mask1_a (5ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.38 sett1 (5bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.39 pr1 (5ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.40 tc1 (5dh-5e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.41 outs1 (5fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.42 peak1 (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.43 ctrl_reg2 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.44 stx_1 (60h-6fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.45 tim4_2 (70h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.46 tim3_2 (71h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.47 tim2_2 (72h - 73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.48 tim1_2 (74h - 75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.49 thrs2_2 (76h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.50 thrs1_2 (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.51 mask2_b (79h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.52 mask2_a (7ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.53 sett2 (7bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.54 pr2 (7ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.55 tc2 (7dh-7e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.56 outs2 (7fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH contents doc id 022405 rev 1 5/53 8.57 peak2 (1ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.58 des2 (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 www.datasheet.co.kr datasheet pdf - http://www..net/
list of tables LIS3DSH 6/53 doc id 022405 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. i2c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. LIS3DSH state machines: sequence of state to execute an algorithm . . . . . . . . . . . . . . . . 15 table 9. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 10. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 14. transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 19 table 15. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19 table 16. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 17. info1 register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. info2 register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19. who_am_i register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 20. control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21. ctrl_reg3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 22. control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 23. ctrl_reg4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 24. ctrl4 odr configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 25. control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 26. control register 5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 27. self-test mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 28. control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 29. control register 6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 30. status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 31. status register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 32. out_t register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 33. out_t register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 34. offset x default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 35. offset y default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 36. offset z default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 37. constant shift x-axis default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 38. constant shift y-axis default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 39. constant shift y-axis default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 40. lc_l default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 41. lc_h default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 42. stat register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 43. stat register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 44. vector filter coefficient register 1 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 45. vector filter coefficient register 2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 46. vector filter coefficient register 3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 47. vector filter coefficient register 4 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 48. threshold value register 3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH list of tables doc id 022405 rev 1 7/53 table 49. out_x_l register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 50. out_x_h register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 51. out_y_l register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 52. out_y_h register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 53. out_z_l register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 54. out_z_h register default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 55. fifo control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 56. fifo mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 57. fifo_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 58. fifo_src register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 59. sm1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 60. sm1 control register structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 61. timer4 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 62. timer3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 63. tim2_1_l default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 64. tim2_1_h default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 65. tim1_1_l default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 66. tim1_1_h default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 67. thrs2_1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 68. thrs1_1 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 69. mask1_b axis and sign mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 70. mask1_b register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 71. mask1_a axis and sign mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 72. mask1_a register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 73. sett1 register structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 74. sett1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 75. pr1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 76. pr1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 77. tc1_l default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 78. tc1_h default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 79. outs1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 80. outs1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 81. peak1 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 82. sm2 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 83. sm2 control register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 84. timer4 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 85. timer3 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 86. tim2_2_l default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 87. tim2_2_h default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 88. tim1_2_l default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 89. tim1_2_h default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 90. thrs2_2 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 91. thrs1_2 default value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 92. mask2_b axis and sign mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 93. mask2_b register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 94. mask2_a axis and sign mask register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 95. mask2_b register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 96. sett2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 97. sett2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 98. pr2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 99. pr2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 100. tc2_l default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 www.datasheet.co.kr datasheet pdf - http://www..net/
list of tables LIS3DSH 8/53 doc id 022405 rev 1 table 101. tc2_h default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 102. outs2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 103. outs2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 104. peak2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 105. des2 default value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 106. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH list of figures doc id 022405 rev 1 9/53 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. i2c slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. LIS3DSH electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8. multiple bytes spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 10. multiple bytes spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. lga-16: mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 www.datasheet.co.kr datasheet pdf - http://www..net/
block diagram and pin description LIS3DSH 10/53 doc id 022405 rev 1 2 block diagram and pin description 2.1 block diagram figure 1. block diagram 2.2 pin description figure 2. pin connection charge amplifier y+ z+ y- z- a x+ x- i2c spi cs scl/spc sda/sdo/sdi sdo/sel int 1/drdy clock trimming circuits reference self test state machines a/d converter int 2 mux and control fifo / logic temp. sensor am10209v1 (top view) direction of the detectable acceleration s 1 5 9 1 3 (bottom view) y 1 x z pin 1 indic a tor vdd_io nc nc scl/spc gnd sda/sdi/sdo cs sel/sdo gnd gnd int1/drdy res int2 gnd vdd res a m10210v1 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH block diagram and pin description doc id 022405 rev 1 11/53 table 2. pin description pin# name function 1 vdd_io power supply for i/o pins 2 nc not connected 3 nc not connected 4 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 5 gnd 0 v supply 6 sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) 7 sel sdo i 2 c address selection spi serial data output (sdo) 8cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 9 int 2 interrupt 2 10 reserved connect to gnd 11 int 1/drdy interrupt 1/ drdy 12 gnd 0 v supply 13 gnd 0 v supply 14 vdd power supply 15 reserved connect to vdd 16 gnd 0 v supply www.datasheet.co.kr datasheet pdf - http://www..net/
mechanical and electrical specifications LIS3DSH 12/53 doc id 022405 rev 1 3 mechanical and electrical specifications 3.1 mechanical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (a) . a. the product is factory calibrated at 2.5 v. the opera tional power supply range is from 1.71 v to 3.6 v. table 3. mechanical characteristics symbol parameter test conditions min. typ. (1) max. unit fs measurement range (2) fs bit set to 000 2.0 g fs bit set to 001 4.0 g fs bit set to 010 6.0 g fs bit set to 011 8.0 g fs bit set to 100 16.0 g so sensitivity fs bit set to 000 0.06 mg/digit fs bit set to 001 0.12 mg/digit fs bit set to 010 0.18 mg/digit fs bit set to 011 0.24 mg/digit fs bit set to 100 0.73 mg/digit tcso sensitivity change vs. temperature fs bit set to 00 0.01 %/c ty o f f typical zero- g level offset accuracy (3) fs bit set to 00 40 m g tcoff zero- g level change vs. temperature max. delta from 25 c 0.5 m g /c an acceleration noise density fs bit set to 00, normal mode, odr = 100 hz 150 u g / sqrt(hz) st self test positive difference (4) 2g range, x,y-axis st2,st1 = [01] see figure 24 140 m g 2g range, z-axis st2,st1 = [01] see figure 24 590 to p operating temperature range -40 +85 c 1. typical specificat ions are not guaranteed. 2. verified by wafer level test and measur ement of initial offset and sensitivity. 3. typical zero- g level offset value after msl3 preconditioning. 4. self-test output change? is defined as: output[mg] (cntl5 st2, st1 bits=01) - output[mg] (cntl5 st2, st1 bits=00) www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH mechanical and electrical specifications doc id 022405 rev 1 13/53 3.2 electrical characteristics @ vdd = 2.5 v, t = 25 c unless otherwise noted (b) . b. the product is factory calibrated at 2.5 v. the ope rational power supply range is from 1.71 v to 3.6 v. table 4. electrical characteristics (1) symbol parameter test conditions min. typ. (2) max. unit vdd supply voltage 1.71 2.5 3.6 v vdd_io i/o pins supply voltage (3) 1.71 vdd+0.1 v idda current consumption in active mode 1.6 khz odr 225 a 3.125 hz odr 11 a iddpdn current consumption in power- down/standby mode 2a vih digital high level input voltage 0.8*vdd_io v vil digital low level input voltage 0.2*vdd_io v voh high level output voltage 0.9*vdd_io v vol low level output voltage 0.1*vdd_io v top operating temperature range -40 +85 c 1. the product is factory calibrated at 2.5 v. the oper ational power supply range is from 1.71 v to 3.6 v. 2. typical specificat ions are not guaranteed. 3. it is possible to remove vdd maintaining vdd_io wit hout blocking the communication buses, in this condition the measurement chain is powered off. www.datasheet.co.kr datasheet pdf - http://www..net/
mechanical and electrical specifications LIS3DSH 14/53 doc id 022405 rev 1 3.3 communication interface characteristics 3.3.1 spi - serial peripheral interface subject to general operating conditions for vdd and top. figure 3. spi slave timing diagram (c) 2. when no communication is on-going, data on sdo is driven by inte rnal pull-up resistor. table 5. spi slave timing values symbol parameter value (1) unit min. max. tc(spc) spi clock cycle 100 ns fc(spc) spi clock frequency 10 mhz tsu(cs) cs setup time 6 ns th(cs) cs hold time 8 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 50 th(so) sdo output hold time 9 tdis(so) sdo output disable time 50 1. values are guaranteed at 10 mhz clock fr equency for spi with both 4 and 3 wires, based on characterization results, not tested in production. c. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output ports. spc cs sd i sd o t su ( cs) t v( so ) t h( so ) t h( si ) t su ( si ) t h( cs) t di s( so ) t c( spc) msb i n msb out lsb out lsb i n (2) (2) (2) (2) (2) (2) (2) (2) www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH mechanical and electrical specifications doc id 022405 rev 1 15/53 3.3.2 i 2 c - inter ic control interface subject to general operating conditions for vdd and top. figure 4. i 2 c slave timing diagram (d) table 6. i 2 c slave timing values symbol parameter i 2 c standard mode (1) i 2 c fast mode (1) unit min. max. min. max. f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0.01 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b ( 2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 2. cb = total capacitance of one bus line, in pf. d. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. sda scl t f(sda) t su(sp) t w(scll) t su(sda) t r(sda) t su(sr) t h(st) t w(sclh) t h(sda) t r(scl) t f(scl) t w(sp:sr) start repeated start stop start www.datasheet.co.kr datasheet pdf - http://www..net/
mechanical and electrical specifications LIS3DSH 16/53 doc id 022405 rev 1 3.4 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v table 7. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin (cs, scl/spc, sda/sdi/sdo, sdo/sel) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 2.5 v) 3000 for 0.5 ms g 10000 for 0.1 ms g a unp acceleration (any axis, unpowered) 3000 for 0.5 ms g 10000 for 0.1 ms g t op operating temperature range -40 to +85 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 2 (hbm) kv this is a mechanical shock sensitive device, improper handling can cause permanent damage to the part. this is an esd sensitive device, improper handling can cause permanent damage to the part. www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH mechanical and electrical specifications doc id 022405 rev 1 17/53 3.5 terminology 3.5.1 sensitivity sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. as the sensor can measur e dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and also time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 3.5.2 zero- g level zero- g level offset (tyoff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. a sensor in a steady-state on a horizontal surface measures 0 g in x axis and 0 g in y axis, whereas the z axis measures 1 g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, data expressed as 2?s complement number). a deviatio n from the ideal value in this case is called zero- g offset. offset is to some extent a result of stress to mems sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero- g level change vs. temperature?. the zero- g level tolerance (tyoff) describes the standard deviation of the range of zero- g levels of a population of sensors. 3.6 functionality 3.6.1 self-test self-test allows to check the sensor functionalit y without moving it. the self-test function is off when the self-test bit (st) is programmed to ?0?. when the self-test bit is programmed to ?1?, an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs exhibit a change in their dc levels which are related to the selected full-scale through the device sensitivity. when self -test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified in table 3 , then the sensor is working properly and the parameters of the interface chip are within the defined specifications. 3.7 sensing element a proprietary process is used to create a surface micro-machined accelerometer. the technology allows to carry out suspended s ilicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. to be compatible with the traditional packaging techniques, a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. www.datasheet.co.kr datasheet pdf - http://www..net/
mechanical and electrical specifications LIS3DSH 18/53 doc id 022405 rev 1 when an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacit ive half bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the capacitor. at steady-state the nominal value of the capacitors are a few pf and when an acceleration is applied, the maximum variation of the capacitive load is in the ff range. 3.8 ic interface the complete measurement chain is made up of a low-noise capacitive amplifier which converts the capacitive unbalancing of the mems sensor into an analog voltage that is finally available to the user through an analog-to-digital converter. the acceleration data may be accessed through an i 2 c/spi interface, therefore making the device particularly suitable for direct interfacing with a microcontroller. the LIS3DSH features a data-ready signal (rdy) which indicates when a new set of measured acceleration data is available, therefore simplifying data synchronization in the digital system that uses the device. 3.9 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero- g level (tyoff). the trimming values are stored inside the device in a non volatile memory. any time the device is turned on, the trimming parameters are downloaded into the registers to be used during the active operation. this allows to use the device without further calibration. www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH application hints doc id 022405 rev 1 19/53 4 application hints figure 5. LIS3DSH electrical connection the device core is supplied through the vdd line while the i/o pins are supplied through the vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f) should be placed as near as possible to pin 14 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 5 ). it is possible to re move vdd maintaining vdd_io without blocking the communication bus, in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data is selectable and accessible through the i 2 c or spi interfaces. when using the i 2 c, cs must be tied high. 4.1 soldering information the lga package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resist ance according to jedec j-std-020. leave ?pin 1 indicator? unconnected during soldering. land pattern and soldering recommendations are available at www.st.com . c s 10 f vdd 100nf gnd vdd_io s el/ s do s da/ s di/ s do int1/drdy s cl/ s pc digit a l s ign a l from/to s ign a l controller. s ign a l? s level s a re defined b y proper s election of vdd_io 1 5 8 1 3 top view 6 9 14 16 9 5 int 2 nc nc am10211v1 www.datasheet.co.kr datasheet pdf - http://www..net/
digital main blocks LIS3DSH 20/53 doc id 022405 rev 1 5 digital main blocks 5.1 state machine the LIS3DSH embeds two state machines able to run a user defined program. the program is made up of a set of instructions that define the transition to successive states. conditional branches are possible. from each state (n) it is possible to have transition to the next state (n+1) or to reset state. transition to reset point happens when ?reset condition? is true; transition to the next step happens when ?next condition? is true. interrupt is triggered when output/stop/continue state is reached. each state machine allows to implement gesture recognition in a flexible way, free-fall, wake-up, 4d/6d orientation, pulse counter and step recognition, click/double click, shake/double shake, face-up/face-down, turn/double turn: code and parameters are loaded by the host into dedicated memory areas for the state program state program with timing based on odr or decimated time possibility of conditional branches table 8. LIS3DSH state machines: sequence of state to execute an algorithm state 1 state 2 next state 3 next state n next reset reset reset reset start output/stop/continue int set am10212v1 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH digital main blocks doc id 022405 rev 1 21/53 5.2 fifo LIS3DSH embeds an acceleration data fifo for each of the three output channels, x, y, and z. this allows a consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. this buffer can work according to four different modes: bypass mode, fifo mode, stream mode and stream-to-fifo mode. each mode is selected by the fifo_mode bits. programmable watermark level, fifo_empty or fifo_full events can be enabled to generate dedicated interrupts on the int1/2 pin. 5.2.1 bypass mode in bypass mode, the fifo is not operational and for this reason it remains empty. for each channel only the first address is used. the remaining fifo slots are empty. 5.2.2 fifo mode in fifo mode, data from x, y, and z channels are stored in the fifo. a watermark interrupt can be enabled in order to be raised when the fifo is filled to the level specified by the internal register. the fifo cont inues filling until it is full. when full, the fifo stops collecting data from the input channels. 5.2.3 stream mode in stream mode, data from the x, y, and z measurement are stored in the fifo. a watermark interrupt can be enabled and set as in the fifo mode. the fifo continues filling until it?s full. when full, the fifo discards the older data as the new arrive. 5.2.4 stream-to-fifo mode in stream-to_fifo mode, data from the x, y, and z measurement are stored in the fifo. a watermark interrupt can be enabled in order to be raised when the fifo is filled to the level specified by the internal register . the fifo continues filling until it?s full. when full, the fifo discards the older data as the new arrive. once trigger event occurs, the fifo starts operating in fifo mode. 5.2.5 retrieve data from fifo fifo data is read through the out_x, out_y and out_z registers. when the fifo is in stream, trigger or fifo mode, a read operation to the out_x, out_y or out_z registers provides the data stored in the fifo. each time data is read from the fifo, the oldest x, y, and z data are placed in the out_x, out_y and out_z registers and both single read and read_burst operations can be used. www.datasheet.co.kr datasheet pdf - http://www..net/
digital interfaces LIS3DSH 22/53 doc id 022405 rev 1 6 digital interfaces the registers embedded inside the LIS3DSH may be accessed through both the i 2 c and spi serial interfaces. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pins. to select/exploit the i 2 c interface, the cs line must be tied high (i.e. connected to vdd_io). 6.1 i 2 c serial interface the LIS3DSH i 2 c is a bus slave. the i 2 c is employed to write data into registers whose content can also be read back. the relevant i 2 c terminology is given in the table below. there are two signals associated with the i 2 c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bi-directional line used for sending and receiving the data to/from the interface. both lines must be connected to vdd_io through an external pull-up resistor. when the bus is free, both lines are high. the i 2 c interface is compliant with fast mode (400 khz) i 2 c standards as well as with normal mode. table 9. serial interface pin description pin name pin description cs spi enable i2c/spi mode selection (1: spi idle mode / i2c communication enabled; 0: spi communication mode / i2c disabled) scl spc i 2 c serial clock (scl) spi serial port clock (spc) sda sdi sdo i 2 c serial data (sda) spi serial data input (sdi) 3-wire interface serial data output (sdo) sel sdo i 2 c address selection spi serial data output (sdo) table 10. serial interface pin description term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH digital interfaces doc id 022405 rev 1 23/53 6.1.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high to low transition on the data line wh ile the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the LIS3DSH is 00111xxb whereas the xx bits are modified by the sel/sdo pin in order to m odify the device address. if the sel pin is connected to the voltage supply, the address is 0011101b, otherwise the address is 0011110b if the sel pin is connected to ground. this solution permits to connect and address two different accelerometers to the same i 2 c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the LIS3DSH behaves as a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge (sak) has been returned, an 8-bit sub-a ddress (sub) is transmitted: the 7 lsb represents the actual register address while the add_inc bit (ctrl_reg6) defines the address increment. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write), the master transmits to the slave with direction unchanged. table 11 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 11. sad+read/write patterns command sad[6:2] sad[1] = sel sad[0] = sel r/w sad+r/w read 00111 1 0 1 00111101 write 00111 1 0 0 00111100 read 00111 0 1 1 00111011 write 00111 0 1 0 00111010 table 12. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak www.datasheet.co.kr datasheet pdf - http://www..net/
digital interfaces LIS3DSH 24/53 doc id 022405 rev 1 data are transmitted in byte format (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. data is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other function, it can hold the clock line, scl low, to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver doesn?t acknowledge the slave address (i.e. it is not able to receive because it is performing some real time function) the data line must be left high by the slave. the master can then abort the transfer. a low to high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in the presented communication format, mak is master acknowledge and nmak is no master acknowledge. 6.2 spi bus interface the LIS3DSH spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs, spc, sdi and sdo. table 13. transfer when master is writing multiple bytes to slave: master st sad + w sub data data sp slave sak sak sak sak table 14. transfer when master is receiving (reading) one byte of data from slave: master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 15. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH digital interfaces doc id 022405 rev 1 25/53 figure 6. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and s hould be captured at the rising edge of spc. both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multip le bytes read/write. bit duration is the time between two falling edges of spc. the first bit (bit 0) starts at t he first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs. bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in the latter case, the chip drives sdo at the start of bit 8. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods are added. when the add_inc(ctrl_reg6) bit is ?0?, the address used to read/write data remains the same for every block. when the add_inc bit is ?1?, the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. c s s pc s di s do rw ad5 ad4 ad 3 ad2 ad1 ad0 di7 di6 di5 di4 di 3 di2 di1 di0 do7 do6 do5 do4 do 3 do2 do1 do0 m s am10129v1 www.datasheet.co.kr datasheet pdf - http://www..net/
digital interfaces LIS3DSH 26/53 doc id 022405 rev 1 6.2.1 spi read figure 7. spi read protocol the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further da ta in multiple byte reading. figure 8. multiple bytes spi read protocol (2-byte example) c s s pc s di s do rw do7 do6 do5 do4 do 3 do2 do1 do0 ad5 ad4 ad 3 ad2 ad1 ad0 m s am101 3 0v1 c s s pc s di s do rw do7do6do5do4do 3 do 2 do 1 do 0 ad5 ad4 ad 3 ad2 ad1 ad0 do 15 do 14 do 1 3 do 12 do 11 do 10 d o9 d o 8 m s am101 3 1v1 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH digital interfaces doc id 022405 rev 1 27/53 6.2.2 spi write figure 9. spi write protocol the spi write command is performed with 16 cl ock pulses. multiple by te write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 -7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. figure 10. multiple bytes spi write protocol (2-byte example) 6.2.3 spi read in 3-wire mode 3-wire mode is entered by setting to ?1? bit sim (spi serial interface mode selection) by internal register. c s s pc s di rw di7 di6 di5 di4 di 3 di 2 di 1 di 0 ad5 ad 4 ad 3 ad2 ad 1 ad0 m s am101 3 2v1 c s s pc s di rw ad5 ad4 ad 3 ad2 ad1 ad 0 di 7 d i6 di 5 d i4 di 3 di 2 di 1 di 0 di 15 d i1 4 di 1 3 di12 di 11 di 10 di 9 di 8 m s am101 33 v1 www.datasheet.co.kr datasheet pdf - http://www..net/
digital interfaces LIS3DSH 28/53 doc id 022405 rev 1 figure 11. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). multiple read command is also available in 3-wire mode. c s s pc s di/o rw do7 do6 do5 do4 do 3 do 2 do 1 do 0 ad5 ad 4 ad 3 ad2 ad1 ad 0 m s am101 3 4v1 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register mapping doc id 022405 rev 1 29/53 7 register mapping table 16 provides a list of the 8/16-bit registers embedded in the device and the related address: table 16. register address map name type register address default comment hex binary info1 r 0d 00001101 0010 0001 information register 1 info2 r 0e 00001110 0000 0000 information register 2 who_am_i r of 00001111 0011 1111 who i am id ctrl_reg3 r/w 23 00100011 - control registers ctrl_reg4 r/w 20 00100000 - ctrl_reg5 r/w 24 00100100 - ctrl_reg6 r/w 25 00100101 - status r 27 00100111 - status data register out_t r 0c 00001100 - temperature output off_x r/w 10 00010000 0000 0000 x-axis offset correction off_y r/w 11 00010001 0000 0000 y-axis offset correction off_z r/w 12 00010010 0000 0000 z-axis offset correction cs_x r/w 13 00010011 0000 0000 constant shift x cs_y r/w 14 00010100 0000 0000 constant shift y cs_z r/w 15 00010101 0000 0000 constant shift z lc_l r/w 16 00010110 0000 0001 long counter registers lc_h r/w 17 00010111 0000 0000 stat r 18 00011000 - interrupt synchronization vfc_1 r/w 1b 00011011 - vector filter coefficient 1 vfc_2 r/w 1c 00011100 - vector filter coefficient 2 vfc_3 r/w 1d 00011101 - vector filter coefficient 3 vfc_4 r/w 1e 00011110 - vector filter coefficient 4 thrs3 r/w 1f 00011111 - threshold value 3 out_x_l r 28 00101000 0000 0000 output registers out_x_h r 29 00101001 out_y_l r 2a 00101010 out_y_h r 2b 00101011 out_z_l r 2c 00101100 out_z_h r 2d 00101101 www.datasheet.co.kr datasheet pdf - http://www..net/
register mapping LIS3DSH 30/53 doc id 022405 rev 1 fifo_ctrl r/w 2e 00101110 0000 0000 fifo registers fifo_src r 2f 00101111 - ctrl_reg1 r/w 21 00100001 0000 0000 sm1 control register st1_x w 40-4f 01000000 01001111 - sm1 code register (x =1-16) tim4_1 w 50 01010000 - sm1 general timer tim3_1 w 51 01010001 - tim2_1 w 52-53 01010010 01010011 - tim1_1 w 54-55 01010100 01010101 - thrs2_1 w 56 01010110 - sm1 threshold value 1 thrs1_1 w 57 01010111 - sm1 threshold value 2 mask1_b w 59 01011001 - sm1 axis and sign mask mask1_a w 5a 01011010 - sm1 axis and sign mask sett1 w 5b 01011011 - sm1 detection settings pr1 r 5c 01011100 - program-reset pointer tc1 r 5d-5e 01011101 01011110 - timer counter outs1 r 5f 01011111 - main set flag peak1 r 19 00011001 - peak value ctrl_reg2 r/w 22 00100010 - s m2 control register st2_x w 60-6f 01100000 01101111 - sm2 code register (x =1-16) tim4_2 w 70 01110000 - sm2 general timer tim3_2 w 71 01110001 - tim2_2 w 72-73 01110010 01110011 - tim1_2 w 74-75 01110100 01110101 - thrs2_2 w 76 01110110 - sm2 threshold value 1 thrs1_2 w 77 01110111 - sm2 threshold value 2 mask2_b w 79 01111001 - sm2 axis and sign mask mask2_a w 7a 01111010 sm2 axis and sign mask sett2 w 7b 01111011 - sm2 detection settings table 16. register address map (continued) name type register address default comment hex binary www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register mapping doc id 022405 rev 1 31/53 pr2 r 7c 01111100 - program-reset pointer tc2 r 7d-7e 01111101 01111110 - timer counter outs2 r 7f 01111111 main set flag peak2 r 1a 00011010 - peak value des2 w 78 01111000 - decimation factor table 16. register address map (continued) name type register address default comment hex binary www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 32/53 doc id 022405 rev 1 8 register description 8.1 info1 (0dh) read only information register. 8.2 info2 (0eh) read only information register. 8.3 who_am_i (0fh) who_am_i register. 8.4 ctrl_reg3 (23h) control register 3. table 17. info1 register default value 00100001 table 18. info2 register default value 00000000 table 19. who_am_i register default value 00111111 table 20. control register 3 dr_en iea iel int2_en int1_en vfilt - strt table 21. ctrl_reg3 register description dr_en drdy signal enable to int1. default value:0 0 = data ready signal not connected, 1 = data ready signal connected to int1 iea interrupt signal polarity. default value:0 0 = interrupt signals active low, 1 = interrupt signals active high iel interrupt signal latching. default value:0 0 = interrupt signals latched, 1 = interrupt signal pulsed int2_en interrupt 2 enable/disable. default value:0 0 = int2 signal disabled, 1 = int2 signal enabled int1_en interrupt 2 enable/disable. default value:0 0 = int1/drdy signal disabled, 1 = int1/drdy signal enabled www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register description doc id 022405 rev 1 33/53 8.5 ctrl_reg4 (20h) control register 4. odr<3:0> is used to set power mode and odr selection. in table 24 (output data rate selection table 22 ) all frequencies available are reported. vfilt vector filter enable/disable. default value:0 0 = vector filter disabled, 1 = vector filter enabled strt soft reset bit 0 = no soft reset, 1 = soft reset (por function) table 21. ctrl_reg3 register description (continued) table 22. control register 4 odr3 odr2 odr1 odr0 bdu zen yen xen table 23. ctrl_reg4 register description odr 3:0 output data rate and power mode selection . default value:0000 (see table 24 ) bdu block data update. default value:0 0:continuos update,1:output registers not updated until msb and lsb reading) zen z axis enable. default value:1 (0:z axis disabled; 1:z axis enabled) ye n y axis enable. default value:1 (0:y axis disabled; 1:y axis enabled) xen x axis enable. default value:1 0=x axis disabled; 1=x axis enabled table 24. ctrl4 odr configuration odr3 odr2 odr1 odr0 odr selection 0000power down 00013.125 hz 00106.25 hz 0 0 1 1 12.5 hz 010025 hz 010150 hz 0110100 hz 0111400 hz 1000800 hz 1 0 0 1 1600 hz www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 34/53 doc id 022405 rev 1 the bdu bit is used to inhibit the output registers update until both upper and lower register parts are read. in default mode (bdu=?0?) the output register values are updated continuously. if for any reason it is not sure whether to read faster than the output data rate it is recommended to set the bdu bit to ?1?. in this way the content of output registers is not updated until both msb and lsb are read avoiding the reading of values related to a different sample time. 8.6 ctrl_reg5 (24h) control register 5. 8.7 ctrl_reg6 (25h) control register 6. table 25. control register 5 bw2 bw1 fscale2 fscale1 fscale0 st2 st1 sim table 26. control register 5 description bw2:bw1 anti-aliasing filter bandwidth. default value: 00 00=800 hz; 01=400 hz; 10:=200 hz; 11:=50 hz) fscale2:0 full-scale selection. default value: 00 000=+/- 2g; 001=+/- 4g; 010=+/- 6g; 011=+/- 8g; 100=+/- 16g st2:1 self-test enable. default value: 00 00=self-test disabled; sim spi serial interface mode selection. default value: 0 0=4-wire interface; 1:=3-wire interface table 27. self-test mode selection st2 st1 self test mode 0 0 normal mode 0 1 positive sign self-test 1 0 negative sign self-test 1 1 not allowed table 28. control register 6 booot fifo_en wtm_en add_ inc p1_ empty p1_wtm p1_over run p2_ boot www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register description doc id 022405 rev 1 35/53 8.8 status (27h) status register. table 29. control register 6 description boot force reboot, cleared as soon as the reboot is finished. active high. fifo_en fifo enable. default value 0. 0=disable; 1=enable wtm_en enable fifo watermark level use. default value 0. 0=disable; 1=enable add_inc register address automatically incremented during a multiple byte access with a serial interface (i 2 c or spi). 0=disable; 1=enable p1_empty enable fifo empty indi cation on int1. default value 0. 0=disable; 1=enable p1_wtm fifo watermark interrupt on int1. default value 0. 0:=disable; 1=enable p1_overrun fifo overrun interrupt on int1. default value 0. 0=disable; 1=enable p2_boot boot interrupt on int2. default value 0. 0=disable; 1=enable table 30. status register zyxor zor yor xor zyxda zda yda xda table 31. status register description zyxor x, y, and z axis data overrun. default value: 0 0=no overrun has occurred; 1=a new set of data has overwritten the previous ones zor z axis data overrun. default value: 0 0=no overrun has occurred; 1=a new set of data for the z-axis has overwritten the pre- vious one yor y axis data overrun. default value: 0 0=no overrun has occurred; 1=a new data for the y-axis has overwritten the previous one xor x axis data overrun. default value: 0 0=no overrun has occurred; 1=a new data for the x-axis has overwritten the previous one zyxda x, y, and z axis new data available. default value: 0 0=a new set of data is not yet available; 1=a new set of data is available zda z axis new data available. default value: 0 0=a new data for the z-axis is not yet available; 1=a new data for the z-axis is available www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 36/53 doc id 022405 rev 1 8.9 out_t (0ch) temperature output register. temperature data (1lsb/deg - 8-bit resolution). the value is expressed as two's complement. 8.10 off_x (10h) offset correction x-axis register,signed value. 8.11 off_y (11h) offset correction y-axis register, signed value. 8.12 off_z (12h) offset correction z-axis register, signed value. yda y axis new data available. default value: 0 0=a new data for the y-axis is not yet available; 1=a new data for the y-axis is available xda x axis new data available. default value: 0 0=a new data for the x-axis is not yet available; 1=a new data for the x-axis is available table 31. status register description (continued) table 32. out_t register temp7 temp6 temp5 temp4 temp3 temp2 temp1 temp0 table 33. out_t register description temp7-temp0 temperature data. table 34. offset x default value 00000000 table 35. offset y default value 00000000 table 36. offset z default value 00000000 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register description doc id 022405 rev 1 37/53 8.13 cs_x (13h) constant shift signed value x-axis register - state machine only. 8.14 cs_y (14h) constant shift signed value y-axis register - state machine only. 8.15 cs_z (15h) constant shift signed value y-axis register - state machine only. 8.16 lc (16h - 17h) 16-bit long-counter register for interrupt state machine programs timing. 01h=counting stopped, 00h=counter full:interrupt available and counter is set to default. values higher than 00h:counting 8.17 stat (18h) interrupt status - interrupt synchronization register. table 37. constant shift x-axis default value 00000000 table 38. constant shift y-axis default value 00000000 table 39. constant shift y-axis default value 00000000 table 40. lc_l default value 00000001 table 41. lc_h default value 00000000 table 42. stat register long syncw sync1 sync2 int_sm1 int_sm2 dor drdy www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 38/53 doc id 022405 rev 1 8.18 vfc_1 (1bh) vector coefficient register 1 for diff filter. 8.19 vfc_2 (1ch) vector coefficient register 2 for diff filter. 8.20 vfc_3 (1dh) vector coefficient register 3 for fsm2 filter. 8.21 vfc_4 (1eh) vector coefficient register 4 for diff filter. table 43. stat register description long 0=no interrupt, 1=long counter (lc) interrupt flag common for both sm syncw synchronization for external host cont roller interrupt based on output data 0=no action waiting from host; 1=acti on from host based on output data sync1 0=sm1 running normally, 1=sm1 stopped and await restart request from sm2 sync2 0=sm2 running normally, 1=sm2 stopped and await restart request from sm1 int_sm1 sm1 - interrupt selection - 1=sm1 interrupt enable; 0: sm1 interrupt disable nt_sm2 sm2 - interrupt selection - 1=sm2 in terrupt enable; 0: sm2 interrupt disable dor data overrun indicates not read data from output register when next data samples measure start; 0=no overrun, 1=data over run data overrun bit is reset when next sample is ready drdy data ready from output register 0=data not ready, 1=data ready table 44. vector filter coefficient register 1 default value 00000000 table 45. vector filter coefficient register 2 default value 00000000 table 46. vector filter coefficient register 3 default value 00000000 table 47. vector filter coefficient register 4 default value 00000000 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register description doc id 022405 rev 1 39/53 8.22 thrs3 (1fh) threshold value e register. 8.23 out_x (28h - 29h) x-axis output register. 8.24 out_y (2ah - 2bh) y-axis output register. 8.25 out_z (2ch - 2dh) z-axis output register. table 48. threshold value register 3 default value 00000000 table 49. out_x_l register default value 00000000 table 50. out_x_h register default value 00000000 table 51. out_y_l register default value 00000000 table 52. out_y_h register default value 00000000 table 53. out_z_l register default value 00000000 table 54. out_z_h register default value 00000000 www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 40/53 doc id 022405 rev 1 8.26 fifo_ctrl (2eh) fifo control register. fmode2:fmode0 = fifo mode selection. wtmp4:wtmp0 = fifo watermark pointer; fifo deep if the watermark is enabled. the fifo trigger is the int2 source. 8.27 fifo_src (2fh) fifo src control register. table 55. fifo control register fmode2 fmode1 fmode0 wtmp4 wtmp3 wtmp2 wtmp1 wtmp4 table 56. fifo mode selection fmode2 fmode1 fmode0 mode 0 0 0 bypass mode. fifo turned off 0 0 1 fifo mode. stop collecting data when fifo is full. 0 1 0 stream mode. if the fifo is full the new sample overwrites the older one 0 1 1 stream mode until trigger is de- asserted, then fifo mode 1 0 0 bypass mode until trigger is de- asserted, then stream mode 101not used 110not used. 1 1 1 bypass mode until trigger is de- asserted, then fifo mode table 57. fifo_src register wtm ovrn_ fifo empty fss4 fss3 fss2 fss1 fss0 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register description doc id 022405 rev 1 41/53 8.28 ctrl_reg1 (21h) sm1 control register. 8.29 stx_1 (40h-4fh) state machine 1 code register stx_1 (x = 1-16). state machine 1 system register is made up of 16, 8- bit registers to implement 16-step op- code. 8.30 tim4_1 (50h) 8-bit general timer (unsigned value) for sm1 operation timing. 8.31 tim3_1 (51h) 8-bit general timer (unsigned value) for sm1 operation timing. table 58. fifo_src register description wtm watermark status. 0=fifo filling is lower than wtm level; 1=fifo filling is equal or higher than wtm level ovrn_fifo overrun bit status. 0=fifo is not comp letely filled; 1=fifo is completely filled empty fifo empty bit. 0=fifo not empty; 1=fifo empty) fss4-fss0 fifo stored data level table 59. sm1 control register hyst2_1 hyst1_1 hyst0_1 - sm1_pin - - sm1_en table 60. sm1 control register structure hyst2_1 hyst1_1 hyst0_1 hysteresis unsigned value to be added or subtracted from threshold value in sm1 default value=000 sm1_pin 0=sm1 interrupt routed to int1, 1=sm1 interrupt routed to int2 pin default value=0 sm1_en 0=sm1 disabled, 1=sm1 enabled default value=0 table 61. timer4 default value 00000000 www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 42/53 doc id 022405 rev 1 8.32 tim2_1 (52h - 53h) 16-bit general timer (unsigned value) for sm1 operation timing. 8.33 tim1_1 (54h - 55h) 16-bit general timer (unsigned value) for sm1 operation timing. 8.34 thrs2_1 (56h) threshold value for sm1 operation. 8.35 thrs1_1 (57h) threshold value for sm1 operation. table 62. timer3 default value 00000000 table 63. tim2_1_l default value 00000000 table 64. tim2_1_h default value 00000000 table 65. tim1_1_l default value 00000000 table 66. tim1_1_h default value 00000000 table 67. thrs2_1 default value 00000000 table 68. thrs1_1 default value 00000000 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register description doc id 022405 rev 1 43/53 8.36 mask1_b (59h) axis and sign mask (swap) for sm1 motion detection operation. 8.37 mask1_a (5ah) axis and sign mask (default) for sm1 motion detection operation. 8.38 sett1 (5bh) setting of threshold, peak detection and flags for sm1 motion detection operation. table 69. mask1_b axis and sign mask register p_x n_x p_y n_y p_z n_z p_v n_v table 70. mask1_b register structure p_x 0=x + disabled, 1=x + enabled n_x 0=x - disabled, 1=x ? enabled p_y 0=y+ disabled, 1=y + enabled n_y 0=y- disabled, 1=y ? enabled p_z 0=z + disabled, 1=z + enabled n_z 0=z - disabled, 1=z ? enabled p_v 0=v + disabled, 1=v + enabled n_v 0=v - disabled, 1=v ? enabled table 71. mask1_a axis and sign mask register p_x n_x p_y n_y p_z n_z p_v n_v table 72. mask1_a register structure p_x 0=x + disabled, 1=x + enabled n_x 0=x - disabled, 1=x ? enabled p_y 0=y + disabled, 1=y + enabled n_y 0=y - disabled, 1=y ? enabled p_z 0=z + disabled, 1=z + enabled n_z 0=z - disabled, 1= z ? enabled p_v 0=v + disabled, 1=v + enabled n_v 0=v - disabled, 1=v ? enabled www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 44/53 doc id 022405 rev 1 8.39 pr1 (5ch) program and reset pointer for sm1 motion detection operation. 8.40 tc1 (5dh-5e) 16-bit general timer (unsigned output value) for sm1 operation timing. table 73. sett1 register structure p_det thr3_sa abs - - thr3_ma r_tam sitr table 74. sett1 register description p_det sm1 peak detection. default value:0 0=peak detection disabled, 1=peak detection enabled thr3_sa default value:0 0=no action, 1=threshold 3 limit val ue for axis and sign mask reset (maskb_1) abs default value:0 0=unsigned thresholds, 1=signed thresholds thr3_ma default value:0 0=no action, 1=threshold 3 limit val ue for axis and sign mask reset (maska_1) r_tam next condition validation flag. default value:0 0=no valid next condition found, 1=valid next condition found and reset sitr default value:0 0=no actions, 1=program flow can be modified by stop and cont commands table 75. pr1 register pp3 pp2 pp1 pp0 rp3 rp2 rp1 rp0 table 76. pr1 register description pp3-pp0 sm1 program pointer address rp3-rp0 sm1 reset pointer address table 77. tc1_l default value 00000000 table 78. tc1_h default value 00000000 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register description doc id 022405 rev 1 45/53 8.41 outs1 (5fh) output flags on axis for interrupt sm1 management. read action of this register, depending on the flag affects sm1 interrupt functions. 8.42 peak1 (19h) peak detection value register for sm1 operation. peak detected value for next condition sm1. 8.43 ctrl_reg2 (22h) state program 2 interrupt mng - sm2 control register. table 79. outs1 register p_x n_x p_y n_y p_z n_z p_v n_v table 80. outs1 register description p_x 0=x + no show, 1=x+ show n_x 0=x - no show, 1=x ? show p_y 0=y + no show, 1=y + show n_y 0=y - no show, 1=y ? show p_z 0=z + no show, 1=z + show n_z 0=z - no show, 1=z ? show p_v 0=v + no show, 1=v + show n_v 0=v - no show, 1=v ? show table 81. peak1 default value 00000000 table 82. sm2 control register hyst2_2 hyst1_2 hyst0_2 - sm2_pin - - sm2_en www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 46/53 doc id 022405 rev 1 8.44 stx_1 (60h-6fh) state machine 2 code register stx_1 (x = 1-16). state machine 2 system register is made up of 16 8-bit registers, to implement 16-step op- code. 8.45 tim4_2 (70h) 8-bit general timer (unsigned value) for sm2 operation timing. 8.46 tim3_2 (71h) 8-bit general timer (unsigned value) for sm2 operation timing. 8.47 tim2_2 (72h - 73h) 16-bit general timer (unsigned value) for sm2 operation timing. table 83. sm2 control register description hyst2_2 hyst1_2 hyst0_2 hysteresis unsigned value to be added or subtracted from threshold value in sm2. default value=000 sm2_pin 0=sm2 interrupt routed to int1, 1=sm2 interrupt routed to int1 pin. default value=0 sm2_en 0=sm2 disabled, 1=sm2 enabled. default value=0 table 84. timer4 default value 00000000 table 85. timer3 default value 00000000 table 86. tim2_2_l default value 00000000 table 87. tim2_2_h default value 00000000 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register description doc id 022405 rev 1 47/53 8.48 tim1_2 (74h - 75h) 16-bit general timer (unsigned value) for sm2 operation timing. 8.49 thrs2_2 (76h) threshold signed value for sm2 operation. 8.50 thrs1_2 (77h) threshold signed value for sm2 operation. 8.51 mask2_b (79h) axis and sign mask (swap) for sm2 motion detection operation. table 88. tim1_2_l default value 00000000 table 89. tim1_2_h default value 00000000 table 90. thrs2_2 default value 00000000 table 91. thrs1_2 default value 00000000 table 92. mask2_b axis and sign mask register p_x n_x p_y n_y p_z n_z p_v n_v table 93. mask2_b register description p_x 0=x + disabled, 1=x + enabled n_x 0=x - disabled, 1=x ? enabled p_y 0=y + disabled, 1=y + enabled n_y 0=y - disabled, 1=y ? enabled p_z 0=z + disabled, 1=z + enabled n_z 0=z - disabled, 1=z ? enabled www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 48/53 doc id 022405 rev 1 8.52 mask2_a (7ah) axis and sign mask (default) for sm2 motion detection operation. 8.53 sett2 (7bh) setting of threshold, peak detection and flags for sm2 motion detection operation. p_v 0=v + disabled, 1=v + enabled n_v 0=v - disabled, 1=v ? enabled table 93. mask2_b register description table 94. mask2_a axis and sign mask register p_x n_x p_y n_y p_z n_z p_v n_v table 95. mask2_b register description p_x 0=x + disabled, 1=x + enabled n_x 0=x - disabled, 1=x ? enabled p_y 0=y + disabled, 1=y + enabled n_y 0=y - disabled, 1=y ? enabled p_z 0=z + disabled, 1=z + enabled n_z 0=z - disabled, 1=z ? enabled p_v 0=v + disabled, 1=v + enabled n_v 0=v - disabled, 1=v ? enabled table 96. sett2 register p_det thr3_sa abs - - thr3_ma r_tam sitr table 97. sett2 register description p_det sm2 peak detection. default value: 0 0=peak detection disabled, 1=peak detection enabled thr3_sa default value: 0 0=no action, 1=threshold 3 limit value for axis and sign mask reset (mask2_b) abs default value: 0 0=unsigned thresholds, 1=signed thresholds thr3_ma default value: 0 0=no action, 1=threshold 3 limit value for axis and sign mask reset (mask2_a) www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH register description doc id 022405 rev 1 49/53 8.54 pr2 (7ch) program and reset pointer for sm2 motion detection operation. 8.55 tc2 (7dh-7e) 16-bit general timer (unsigned output value) for sm2 operation timing. 8.56 outs2 (7fh) output flags on axis for interrupt sm2 management. read action of this register, depending on the flag affects sm2 interrupt functions. r_tam next condition validation flag. default value:0 0=no valid next condition found, 1=valid next condition found and reset sitr default value: 0 0=no actions, 1=program flow can be modified by stop and cont commands table 97. sett2 register description table 98. pr2 register pp3 pp2 pp1 pp0 rp3 rp2 rp1 rp0 table 99. pr2 register description pp3-pp0 sm2 program pointer address rp3-rp0 sm2 reset pointer address table 100. tc2_l default value 00000000 table 101. tc2_h default value 00000000 table 102. outs2 register p_x n_x p_y n_y p_z n_z p_v n_v table 103. outs2 register description p_x 0=x + no show, 1=x + show n_x 0=x - no show, 1=x ? show www.datasheet.co.kr datasheet pdf - http://www..net/
register description LIS3DSH 50/53 doc id 022405 rev 1 8.57 peak2 (1ah) peak detection value register for sm2 operation. peak detected value for next condition sm2. 8.58 des2 (78h) decimation counter value register for sm2 operation. registers marked as ? reserved ? must not be changed. the writing to those registers may cause permanent damages to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. p_y 0=y + no show, 1=y + show n_y 0=y - no show, 1=y ? show p_z 0=z + no show, 1=z + show n_z 0=z - no show, 1=z ? show p_v 0=v + no show, 1=v + show n_v 0=v - no show, 1=v ? show table 103. outs2 register description table 104. peak2 default value 00000000 table 105. des2 default value 00000000 www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH package information doc id 022405 rev 1 51/53 9 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 12. lga-16: mechanical data and package dimensions di mensi ons ref . mm i nch mi n. typ. m ax. m i n. typ. m ax. a1 1.000 0.0 39 4 a2 0.7 8 50.0 3 0 9 a 3 0.200 0.007 9 d1 2. 8 50 3 .000 3 .150 0.1122 0.11 8 1 0.1240 e1 2. 8 50 3 .000 3 .150 0.1122 0.11 8 1 0.1240 l1 1.000 1.060 0.0 39 4 0.0417 l2 2.000 2.060 0.07 8 70.0 8 11 n1 0.500 0.01 9 7 n2 1.000 0.0 39 4 m 0.040 0.100 0.160 0.0016 0.00 39 0.006 3 p1 0. 8 75 0.0 3 44 p2 1.275 0.0502 t1 0.2 9 00. 3 50 0.410 0.0114 0.01 38 0.0161 t2 0.1 9 0 0.250 0. 3 10 0.0075 0.00 98 0.0122 d 0.150 0.005 9 k 0.050 0.0020 lga-16 ( 3 x 3 x1.0mm) land grid array packa g e out l i ne and 7 983 2 3 1 mechani cal dat a www.datasheet.co.kr datasheet pdf - http://www..net/
revision history LIS3DSH 52/53 doc id 022405 rev 1 10 revision history table 106. document revision history date revision changes 26-oct-2011 1 initial release. www.datasheet.co.kr datasheet pdf - http://www..net/
LIS3DSH doc id 022405 rev 1 53/53 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com www.datasheet.co.kr datasheet pdf - http://www..net/

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